The present disclosure relates generally to the fabrication of semiconductor devices, and more particularly, to semiconductor-on-insulator chips incorporating partially-depleted, fully-depleted, and multiple-gate devices.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore""s Law), which means that the number of devices on a chip doubles every two years. Today""s fabrication plants are routinely producing devices having 0.35 xcexcm and even 90 nm feature sizes.
The desire for higher performance circuits has driven the development of high-speed sub-100 nanometer (nm) silicon-on-insulator (SOI) complementary metal-oxide- semiconductor (CMOS) technology. In SOI technology, metal-oxide semiconductor field-effect transistors (MOSFETs) are formed on a thin layer of silicon overlying a layer of insulating material such as silicon oxide. Devices formed on SOI offer many advantages over their bulk counterparts, including reduced junction capacitance, absence of reverse body effect, soft-error immunity, full dielectric isolation, and absence of latch-up. SOI technology therefore enables higher speed performance, higher packing density, and reduced power consumption.
There are two types of SOI devices: partially-depleted SOI (PD-SOI) devices, and fully-depleted (FD-SOI) devices. A PD-SOI MOSFET is one in which the body thickness is thicker than the maximum depletion layer width Wd.max, and a FD-SOI MOSFET is one in which the body thickness is thinner than Wd.max.
It is noticed that remarkable progress has recently been achieved in PD-SOI technology. Although PD-SOI devices have the merit of being highly manufacturable, significant design burden is faced by its users because of floating body effects. In PD-SOI devices, charge carriers generated by impact ionization near the drain/source region accumulate near the source/drain region of the transistor. When sufficient carriers accumulate in the floating body, which is formed right below the channel region, the body potential is effectively altered. Floating body effects occur in PD-SOI devices because of charge build-up in the floating body region. This results in kinks in the device current-voltage (I-V) curves, thereby degrading the electrical performance of the circuit. In general, the body potential of a PD-SOI device may vary during static, dynamic, or transient device operation, and is a function of many factors like temperature, voltage, circuit topology, and switching history. Therefore, circuit design using PD-SOI devices is not straightforward, and there is a significant barrier for the adoption of PD-SOI technology or the migration from bulk-Si design to PD-SOI design.
One traditional way to suppress floating body effects in PD-SOI devices is to provide an extra electrical connection by adding a contact to the body for collection of current due to impact ionization. Various methods of making a contact to the body of a SOI transistor are known, but various disadvantages are known to be associated with these methods. One method for the suppression of the SOI floating-body effects is to use a linked-body device structure. However, the method is limited by a high body contact resistance. Blake et al., in U.S. Pat. No. 4,946,799, described a process for making a body node to source node connection, where a contact region of the same conductivity type as the body node is formed within the source region in a self-aligned fashion, thus eliminating the floating body effects. However, the method of Blake et al. results in a reduced amount of current that can only be handled for a given transistor width. In U.S. Pat. No. 6,387,739 issued to G. E. Smith III et al, a method for forming a body contact structure for SOI transistor is described. This method, however, takes up an additional amount of space or layout area.
Another way of avoiding floating body effects in SOI devices is to adopt a fully-depleted SOI (FD-SOI) technology. FD-SOI devices do not suffer from floating-body effects due to the fact that the body is fully-depleted. FD-SOI technology is therefore design-friendly since floating-body effects need not be accounted for in circuit design. In a FD-SOI technology, devices with a low body-doping and/or a thin body thickness are used. For good control of short-channel effects in ultra-scaled devices, the device body thickness is usually reduced to less than one third of gate length. Such a thin body thickness would require raised source/drain technology for series resistance reduction. However, raised source/drain formation, currently performed by selective epitaxy, is immature, expensive, pattern-density dependent, and may result in reduced manufacturing yield. In addition, SOI substrates with uniform ultra-thin Si films, as required for the manufacture of FD-SOI devices with ultra-thin body, is currently unavailable.
What is needed is a method and system to overcome the shortcomings of the prior art, and to provide a highly manufacturable PD-SOI-like technology that produces FD-SOI type devices to eliminate floating body effects.
The present disclosure provides a system and method for forming devices on an insulator material. First, a semiconductor depletion material is formed with a predetermined height and width overlying a predetermined portion of the substrate to form an active region. An isolation material formed on top of the substrate surrounding the active region so as to bury a bottom portion of the active region therein, thereby exposing a top portion of the active region. A gate dielectric layer is deposited for covering the exposed the top and two sidewalls of the top portion of the active region, and at least one gate electrode is then formed on top of the gate dielectric layer and extending through two sidewalls thereof to reach the isolation material.
In one example, a silicon-on-insulator (SOI) chip is formed with a silicon layer of a predetermined thickness overlying an insulator layer at a predetermined location. A fully-depleted SOI (FD-SOI) device is formed on a first portion of the semiconductor layer using a partially depleted SOI (PD-SOI) technology based process, wherein an active region of the FD-SOI device is isolated and has two top round edges. On the same silicon layer, a partially-depleted SOI (PD-SOI) device is also formed on a second portion of the silicon layer.